Chia-Lin Yang

       Professor
       Department of Computer Science and Information Engineering
       National Taiwan University
       No. 1, Roosevelet Rd., Sec 4
       Taipei, Taiwan 106, R.O.C
       Tel: 886-2-23625336
       Fax: 886-2-23628167
       Email: yangc@csie.ntu.edu.tw

Research LAB: Embedded Computing Lab

Research Interests:

  • Storage system for big data analytics
     
  • Compute-in-Memory Architecture Design
     
  • AI-Enabled IoT
     

Employment History:   

· Director, Delta-NTU Joint Research Lab, 2020~current

· Chief Scientist, Taiwan AI Labs, 2019~2020

·         Director of Graduate Institute of Networking and Multimedia, 2016 ~ 2019

·         Director, Office of International Affairs, College of EECS, 2013 ~ 2014

·         Associate Chair, Department of Computer Science and Information Engineering, 2012 ~ 2013

·         Professor, Department of Computer Science and Information Engineering, 2009 ~ present

·         Associate Professor, Department of Computer Science and Information Engineering, 2004 ~ 2009

·         Assistant Professor, Department of Computer Science and Information Engineering, 2001 ~ 2004

·         Software Engineer, VLSI Technology Corp., 1993-1995

Education:

·         Ph.D., Computer Science, Duke University, 2001

·         M.S., Computer Science, University of Texas at Austin, 1992

·         B.Ed., Information & Computer Education, National Taiwan Normal University, 1989

Honors and Awards:

§  2018 Outstanding Electrical Engineering Professor, Chineses Electrical Engineering Asociation

§  2014 NTU EECS Academic Contribution Award

§  2013 IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT) Best Paper Nomination

§  2010 IBM Faculty Award

§  2009 ACM/IEEE International Conference on Computer-Aided Design (ICCAD'09)  Best Paper Nomination

§  2009 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '09)   Best Paper Award.

§  2005 IBM Faculty Award

§  2004 ACM/IEEE  Asia and South Pacific Design Automation Conference (ASP-DAC’04) Best Paper Nomination

§  2003 NTU Excellent Teaching Award

§  2000-2001 Intel Foundation Graduate Fellowship Award

 

 

Professional Activities：

§   Journal Editorship

l Associate Editor, ACM Transactions on Computer Architecture and Code Optimizations, 2020~current

l  Assoicate Editor, ACM Transactions on Embedded Compputing Systems, 2020~current

l  Associate Editor, IEEE Transactions on Computer-Aided Design, 2018 ~ current

l  Associate Editor, IEEE Computer Architecture Letter, 2018 ~ current

l  Editorial Board, IEEE Design and Testing, 2017~ current

§  Organizing Committees

l Executive Committee, DAC 2022

l 2019 ~ current, Steerging Committee, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)

l 2017 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), General Co-Chair

l 2016 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Program Co-Chair

l   2016 ACM/IEEE International Symposium on Microarchitecture, General Co-Chair

l   Design Conte

l   2014 ACM International Symposium of Computer Architecture (ISCA), Publicility Chair

§  Technical Program Committees

l   2021 IEEE International Symposium on High-Performance Computer Architecture, Program Committee Member (External)

l   2021  International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Program Committee Member

l   2020 SIGDA Outstanding Ph.D Dissertation Award Committee

l   2020 The 1st Instruction Prefetching Championship (IPC1), Program Committee Member

l   2020 IEEE/ACM Internatioanl Conference on Computer-Aided Design (ICCAD), 2020 ACM/IEEE International Symposium on Microarchitecture, Program Committee Member

l   2019 IEEE/ACM Internatioanl Conference on Computer-Aided Design (ICCAD), Track Chair

l   2019 ACM/IEEE International Symposium of Computer Architecture (ISCA) Program Committee Member

l   2019 IEEE High Performance Computer Architecture (HPCA), Program Committee Member

l   2019 ACM Architectural Support for Programming Languages and Operating Systems (ASPLOS)

l   2017 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), General Chair

l   2014~2017 ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), TPC Track Chair

l   2017~2019 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Program Committee Member

l   2014~2017 Design Automation and Testing in Europe (Date), Program Committee Member

l   2017 ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), TPC Track Chair

l   2016 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Program Chair

l   2016 ACM/IEEE International Symposium on Microarchitecture, General Chair

l   2016 ACM/IEEE International Symposium on Computer Architecture (ISCA), Program Committee Member

l   2015 ACM/IEEE Design Automation Conference (DAC), Program Committee Member

l   2015 Usenix ATC (Annual Technical Conference), Program Committee Member

l   Guest Editor, IEEE Design and Testing, Special Issue on Cloud Computing for Embedded Systems, 2014

l   2014 ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), TPC Track Chair

l   2014 ACM International Symposium of Computer Architecture (ISCA), Publicility Chair

l   2014 ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (ISSS+CODES), Program Committee Member

l   2013 ~ 2015 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Program Committee Member

l   2013 ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (ISSS+CODES), Program Committee Member

l   2013 International Conference on Parallel Processing (ICPP), Program Committee Member

l   2013 IEEE International Symposium on Workload Characterization (ISSWC), Program Committee Member

l   2012 IEEE High Performance Computer Architecture (HPCA), Program Committee Member

l   2012 ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), TPC Track Chair

l   2012 ACM/IEEE Design Automation and Testing in Europe (Date), Program Committee Member

l   2011 IEEE International Parallel & Distributed Processing Symposium (IPDPS), Program Committee Member

l   2011~2012 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Design Contest Chair

l   2009-2013 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Program Committee Member

l   2008-2010 ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC),  Program Committee Member

l   2006-2008 IEEE International Conference on Computer Design (ICCD), Program Committee Member

l   2009 IEEE Annual Symposium on VLSI, Program Committee Member

l   2007-2009 IEEE International Conference on Embedded and Real-Time Computing and Applications, Program Committee Member

l   2008 IEEE International Conference on Field-Programmable Technology, Session Chair & Local Arrangement Co-Chair

l   2008 10th Workshop on Computer Techniques for High-Performance Computing, Program Chair

l   2007 IFIP International Conference on Embedded and Ubiquitous Computing, Program Committee Member & Local Arrangement Co-Chair

 

 

 

 

Conference PAPERs

n  Robust Brain-Inspired Computing: On the Reliability of Spiking Neural Network Using Emerging Non-Volatile Synapses, Ming-Liang Wei, Hussam Amrouch, Cheng-Lin Sung, Hang-Ting Lue, Chia-Lin Yang, Keh-Chung Wang, Chih-Yuan Lu, in Proceedings of the 59th Annual IEEE International Reliability Physics Symposium (IRPS 2021), Virtual on-line, March 2021 : 1-8

n  Analyzing the Interplay Between Random Shuffling and
Storage Devices for Efficient Machine Learning, Zhi-Lin Ke, Hsiang-Yun Cheng,
Chia-Lin Yang, Han-Wei Huan, in Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Virtual on-line,  March, 2021 : 276-287

n  Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks, Qilin Zheng, Zongwei Wang, Zishun Feng, Bonan Yan, Yimao Cai, Ru Huang, Yiran Chen, Chia-Lin Yang, Hai Helen Li, in Proceedings of the 58th Annual Design Automation Conference (DAC 2020), San Francisco, July 2020 : 1-6

n  The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper Jörg Henkel, Hussam Amrouch, Martin Rapp, Sami Salamin, Dayane Reis, Di Gao, Xunzhao Yin, Michael T. Niemier, Cheng Zhuo, Xiaobo Sharon Hu, Hsiang-Yun Cheng, Chia-Lin Yang, In Proceedings of  IEEE/ACM International Conference on Computer-Aided Design, Westminster,Colorado, USA, November 2019 : 1-6

n  Iotbench: A Benchmark Suite for Intelligent Internet of Things Edge Devices, Chien-I Lee, Meng-Yao Lin, Chia-Lin Yang, Yen-Kuang Chen:, In Proceedings of IEEE International Conference on Image Procssing (ICIP), Taipei, Taiwan, September, 2019 170-174

n  Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks,Tzu-Hsien Yang, Hsiang-Yun Cheng,Chia-Lin Yang,I-Ching Tseng, Han-Wen Hu,Hung-Sheng Chang,Hsiang-Pang Li, in Proceedings of ACM/IEEE International Symposium on Computer Architecture (ISCA),Phonex, AZ, June, 2019 236-249

n  Fair Down to the Device: A GC-Aware Fair Scheduler for SSD Cheng Ji, Lun Wang, Qiao Li, Congming Gao, Liang Shi, Chia-Lin Yang, Chun Jason Xue, in Proceedings of 7th IEEE Non-Volatile Memory System and Applications Symposium (NVMSA’19), Hangzhou, China, August, 2019 : 1-6

n  DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning, Meng-Yao Lin, Hsiang-Yun Cheng, Wei-Ting Lin, Tzu-Hsien Yang, I-Ching Tseng, Chia-Lin Yang, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang, in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, San Diego, CA, USA, November 2018 : 31

n  Active Forwarding: Eliminate IOMMU Address Translation for Accelerator-Rich Architectures, Hsueh-Chun Fu, Po-Han Wong, Chia-Lin Yang, in Proceedings of the 53th Annual Design Automation Conference (DAC’18), San Francisco, CA, USA, June, 2018 : 112:1-112:6

n  Analyzing OpenCL 2.0 Workloads Using a Heterogeneous CPU-GPU Simulator,
Li Wang, Ren-Wei Tsai, Shao-Chung Wang, Kun-Chih Chen, Po-Han Wang, Hsiang-Yun Cheng, Yi-Chung Lee, Sheng-Jie Shu, Chun-Chieh Yang, Min-Yih Hsu, Li-Chen Kan, Chao-Lin Lee, Tzu-Chieh Yu, Rih-Ding Peng, Chia-Lin Yang, Yuan-Shin Hwang, Jenq Kuen Lee, Shiao-Li Tsao, Ming Ouhyoung, in Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS’17), Santa Rosa, CA, April 2017 : 127-128

n  Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach, Chun-Hao Lai, Jishen Zhao, Chia-Lin Yang, in Proceedings of the 53th Annual Design Automation Conference (DAC’17), Austin, Texas, USA, June, 2017 : 5:1-5:6

n  Enabling Fast Preemption via Dual-Kernel Support on GPUs, Li-Wei Shieh, Kun-Chih Chen, Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang, in Proceedings of Asia South Pacific Design Automation Conference (ASP-DAC’17), Tokyo, Jan., 2017 : 121-126

n  Latency Sensitivity-Based Cache Partitionig for Heterogeneous Multi-core Architecture, Po-Han Wong, Cheng-Hsuan Li, Chia-Lin Yang, in Proceedings of the 52th Annual Design Automation Conference (DAC’16), Austin, Texas, USA, June, 2016 : 5:1-5:6

n  MCSSim: A Memory Channel Storage Simulator, Renhai Chen, Zili Shao, Chia-Lin Yang, Tao Li, in Proceedings of Asia South Pacific Design Automation Conference (ASP-DAC’16), Macao, Feb., 2016 : 153-158

n  Fine-grained Write Scheduling for PCM Performance Improvement under Write Power Budget, Chun-Hao Lai, Shun-Chih Yu, Chia-Lin Yang, Hsiang-Pang Li, in Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED ‘15), Rome, Italy, September, 2015 : 19-24

n  Improving DRAM Latency with Dynamic Asymmetric Subarray, Shih-Lien Lu, Ying-Chen Lin, Chia-Lin Yang,  in Proceedings of IEEE International Symposium on Microarchitecture (Micro’15), Waikiki, Hawaii,USA, December : 255-266

n  A Buffer Cache Architecture for Smartphones with Hybrid DRAM/PCM Memory, Ye-Jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang, In Proceedings of 4th IEEE Non-Volatile Memory System and Applications Symposium (NVMSA’16), Hong Kong, 2015 : 1-6

n  Thermal/performance Characterization of CMPs with 3D-stacked DRAMs under Synergistic Voltage-Frequency Control of Cores and DRAMs, Yi-Jung Chen, Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu, in Proceedings of  ACM Research in Adaptive and Convergent Systems (RACS’15),  2015 : 430-436

n  Full System Simulation Framework for Integrated CPU/GPU Architecture, Po-Han Wang, Gen-Hong Liu, Jen-Chieh Yeh, Tse-Min Chen, Hsu-Yao Huang, Chia-Lin Yang, Shih-Lien Liu, James Greensky, in Proceedings of IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT), Hsinchu, Taiwan, April, 2014 : 1-4

n  NVM Duet: Unified Working Memory and Persistent Store Architecture, Ren-Shuo Liu, De-Yu Shen, Chia-Lin Yang*, Shun-Chih Yu, Cheng-Yuan Michael Wang, 2014, March, in Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '14), Salt Lake City, USA. 455-470

n  Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs, Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li, in Proceedings of the 50th Annual Design Automation Conference (DAC’14), San Fransisco, USA, June, 2014 : 145:1-145:6

n  Thermal Coupling Aware Task Migration using Neighboring Core Search for Many-core Systems, Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang, VLSI-DAT 2013: 1-4

n  Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs, Ping-Sheng Lin, Yi-Jung Chen, Chia-Lin Yang, Yi-Chang Lu, in Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED ‘13), WIP, Beijing, China, September, 2013 : 304

n  DuraCache: A Durable SSD Cache Using MLC NAND Flash, Ren-Shuo Liu, Chia-Lin Yang, Cheng-Hsuan Li, Geng-You Chen, in Proceedings of the 50th Annual Design Automation Conference (DAC’13), Austin, USA, June, 2013 : 166:1-166:6

n  Distributed Memory Interface Synthesis for Network-on-Chips with 3-D Stacked DRAMs, Yi-Jung Chen, Chia-Lin Yang, Jian-Jia Chen, in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD’12),  San Jose, USA, November, 2012 : 458-465

n  SECRET: Selective Error Correction for Refresh Energy reducTion in DRAMs, Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang and Michael Wang, in Proceedings of the IEEE International Conference on Computer Design (ICCD’12), Sep., 2012 : 67-74

n  Age-based PCM wear leveling with nearly zero search cost, Chi-Hao Chen, Pi-Cheng Hsiu, Tei-Wei Kuo, Chia-Lin Yang, Cheng-Yuan Michael Wang, in Proceedings of ACM/IEEE Design Automation Conference (DAC '12), San Franciso, CA, June, 2012 : 453-458

n  A cycle-level SIMT-GPU simulation framework, Po-Han Wang, Chien-Wei Lo, Chia-Lin Yang, Yu-Jung Cheng, in Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS’12), New Brunswick, NJ, April 2012 : 114-115

n  Optimizing NAND Flash-Based SSDs via Retention Relaxation, Ren-Shuo Liu, Chia-Lin Yang, Wei Wu, in Proceedings of the 10th USENIX Conference on File and Storage Technologies (FAST '12), San Jose, CA, USA, Feb., 2012 : 11

n  Memory Access Aware Power Gating for MPSoCs, Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang and Naehyuck Chang, in Proceedings of Asia South Pacific Design Automation Conference (ASP-DAC), Feb., 2012 : 121-126

n  A SAT-based routing algorithm for cross-referencing biochips, Ping-Hung Yuh, Cliff Chiung-Yu Lin, Tsung-Wei Huang, Tsung-Yi Ho, Chia-Lin Yang, Yao-Wen Chang, in Proceedings of the IEEE System Level Interconnect Prediction (SLIP), June, 2011 : 1-7

n  Memory Latency Reduction via Thread Throttling, H. -Y Cheng, C.-H  Lin, J. Lee , C.-L Yang, in Proceedings of IEEE International Symposium on Microarchitecture (Micro’10), Atlanta, Georgia, USA, December : 53-64

n  Hierarchical Memory Scheduling for Multimedia MPSoCs, Y.-J Lin, C.-L Yang, T.-J Lin, J.-W Huang and N. Chang, in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD’2010) , San Jose, USA, Nov, 2010 : 190-196

n  Parallelization and Characterization of GARCH Option Pricing on GPUs, R.-S. Liu, Yun-Cheng Tsai, Chia-Lin Yang, Proceedings of IEEE International Symposium on Workload Characterization (IISWC’2010) , Atlanta, Georgia, USA, December : 1-10

n  Dynamic Thermal Management for Networked Embedded Systems under Harsh Ambient Temperature Variation, Sangyoung Park, Jian-Jia Chen, Donghwa Shin, Younghyun Kim, Chia-Lin Yang, Naehyuck Chang (ISLPED’10), Austin, TX, USA, August, 2010 : 289-294

n  PM-COSYN: PE and Memory Co-Synthesis for MPSoCs hermal Modeling for 3D-ICs with Integrated Microchannel Cooling, Y.-J. Chen, C.-L. Yang and P.-H. Wang, in Proceedings of the Design, Automation and Test in Europe, Feburary (DATE '10), Dresden, Germany, March, 2010 : 1590-1595

n  Thermal Modeling for 3D-ICs with Integrated Microchannel Cooling, H. Mizunuma, C.-L. Yang, Y.-C. Lu,  in Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD '09) , San Jose, CA, USA, November,  2009, Best  Paper Nomination. 256-263

n  PPT: Joint Performance/Power/Thermal Management of DRAM Memory for Multi-Core Systems, C.-H. Lin,  C.-L. Yang, K.-J. King, in Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '09), San Francisco, CA, USA, August, 2009, Best Paper Award. 93-98

n  Content-Aware Energy Prediction for Video Streaming in Mobile Devices, Y.-C. Li, H.-H. Li, H.-L. Li, C.-L. Yang, in Proceedings of IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT), Hsinchu, Taiwan, April, 2009 :

n  A Progressive-ILP Based Routing Algorithm for Cross-Referencing Biochips, P.-H. Yuh, S. Sapatnekar, C.-L. Yang, and Y.-W. Chang, in Proceedings of ACM/IEEE Design Automation conference (DAC’08), Anaheim, CA, USA, June, 2008 (EI) (acceptance rate: 23%, 147/239). 284-289

n  Thermal coupling aware task migration using neighboring core search for many-core systems, Shao-Yi Chien, Chi-Sheng Shih, Mong-Kai Ku, Chia-Lin Yang, Yao-Wen Chang, Tei-Wei Kuo, Liang-Gee Chen, ICME 2007: 9  2013

n  Efficient obstacle-avoiding rectilinear steiner tree construction, Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang, ISPD 2007 : 127-134

n  Post Placement Leakage Optimization for Partially Dynamic Reconfigurable FPGAs, C-F. Li, P-H. Yuh. C-L. Yang and Y-W. Chang, in Proceedings of ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED '07), Portland, USA, August, 2007 : 92-97

n  Bioroute: A Network-Flow Based Routing Algorithm for Digital Microfluidic Biochips, P.-H. Yuh, C.-L. Yang, ans Y.-W. Chang, in Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD'07),San Jose, CA, November, 2007 : 752-757

n  Cache Leakage Control Mechanism for Hard Real-Time Systems, J.-W. Chi, Y.-J. Chen, and C.-L. Yang, in Proceedings of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES '07), Saizburg, Austria, September, 2007 : 248-256

n  Energy-Efficient Real-Time Task Scheduling with Task Rejection, J.-J. Chen, T.-W. Kuo, C.-L. Yang and K.-J. King, in Proceedings of Design, Automation & Test in Europe (DATE '07), Nice, France, April, 2007 : 1629-1634

n  An Architectural Co-Synthesis Algorithm for Energy-Aware Network-on-Chip Design, W.-H. Hung, Y.-J. Chen, C.-L. Yang, Y.-S. Chang, Alan P. Su, in Proceedings of 22nd Annual ACM Symposium on Applied Computing (SAC '07), Seoul, Korea, March, 2007 : 680-684

n  Branch Behavior Characterization for Multimedia Applications, Chia-Lin Yang, Shun-Ying Wang, Yi-Jung Chen, Asia-Pacific Computer Systems Architecture Conference 2006 : 523-530

n  An Energy-Efficient Virtual Memory System with Flash Memory as the Secondary Storage, H.-W. Tseng, H.-L. Li, and C.-L. Yang, in Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '06), Tegernsee, Germany, October, 2006 : 418-423

n  Hierarchical Value Cache Encoding for Off-chip Data Bus, C.-H. Lin and C.-L. Yang, in Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '06), Tegernsee, Germany, October, 2006 : 143-146

n  Placement of Digital Microfluidic Biochips Using the T-Tree Formuation, P-H. Yuh, C.-L. Yang,and Y.-W. Changn, in Proceedings of ACM/IEEE Design Automation Conference (DAC '06), San Franciso, CA, July, 2006 : 931-934

n  A Space Efficient Caching Mechanism for Flash Memory Address Translation, C.-H. Wu, T.-W Kuo and C.-L Yan, in Proceedings of IEEE International Symposium on Object and component-oriented Real-time distributed Computing (ISORC '06), Gyeongju, Korea, April, 2006 : 64-71

n  Cache Leakage Management for Multi-programming Workloads, C.-. Chen, C.-L. Yang, S.-H. Hung, in Proceedings of Asia-Pacific Computer Systems Architecture Conference (ACSAC '05), Singapore, October, 2005 : 736-749

n  Reconfigurable Platform for Content Science Research, C.-S. Shih, C.-L. Yang, M.-K. Ku, T.-W. Kuo, S.-Y. Chien,Y.-W. Chang, L.-G. Chen, in Proceedings of Embedded and Real-Time Computing Systems and Applications (RTCSA'05), Hong Kong, August, 2005 : 481-486

n  Joint Exploration of Architectural and Physical Design Spaces with Thermal Consideration, Y.-W. Wu, C.-L. Yang, P.-H. Yuh,Y.-W. Chang, in Proceedings of the 2005 international symposium on Low power electronics and design (ISLPED '05), Sandiego, USA, August, 2005 : 123-126

n  Phase-Aware I-Cache Size Synthesis with QoS Consideration, Y.-J. Chen, C.-L. Yang, E.-K. Lin, in Proceedings of Asia and South Pacific International Conference on Embedded SoCs (ASPICES '05), Banagolore, India, July, 2005

n  Workload Characterization of the H.264/AVC Decoder, C.-L. Yang, in Proceedings of the 5th IEEE Pacific-Rim Conference on Multimedia (PCM '04), Springer-Verlag, Japan, November, 2004 : 957-966

n  Temporal Floorplanning using T-tree Formulation, P.-H. Yu, C.-L. Yang andY.-W. Chang, in Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD'04), San Jose, November, 2004 : 300-305

n  Energy-Efficient Flash Memory Storage Systems with an Interrupt Emulation Mechanism, C.-H. Wu, T.-W Kuo and C.-L Yang, in Proceedings of IEEE/ACM International Conference on Hardware/Software odesign and System Synthesis (CODES + ISSS '04),Stockholm, Sweden, September, 2004 : 134-139

n  HotSpot Cache: Joint Temporal and Spatial Locality Exploitation for I-Cache Energy Reduction, C.-L. Yang and C.-H. Lee, in Proceedings of IEEE/ACM Internatioanl Symposium on Low Power Electronics and Design (ISLPED '04), NewPort Beach, California, August, 2004 : 114-119

n  Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations, J.-J. Chen, H.-R. Hsu, K.-H. Chuang, C.-L. Yang, A.-C. Pang and T.-W. Kuo, in Processdings of 16th Euromicro Conferecne on Real-Time Systems (ECRTS'04), Catania, Italy, June, 2004 : 101-108

n  Profit-Driven Uniprocessor Scheduling with Energy and Timing Constraints, J.-J. Chen, T.-W. Kuo and C.-L. Yang, in Proceedings of the in Proceedings of 19nd Annual ACM Symposium on Applied Computing (SAC '04), Nicosia, Cyprus, March, 2004 : 834-840

n  Value-Conscious Cache: Simple Technique for Reducing Cache Access Power, Y.-J. Chang, C.-L. Yang and F.-P. Lai, in Proceedings of the Design, Automation and Test in Europe, Feburary (DATE '04), Paris, France, February, 2004 : 16-21

n  Temporal Floorplanning Using 3D-subTCG, P.-H. Yuh, C.-L. Yang andY.-W. Chang, in Proceedings of 9th Asia and South Pacific Design Automation Conference (ASP-DAC'04), Japan, Janury, 2004 : 725-730

n  Smart Cache: An Energy-Efficient D-Cache for a Software MPEG-2 Video Decoder, C.-L. Yang, H.-W. Tseng and C.-C. Ho, in Proceedings of the IEEE ICICS-PCM, Singapore, December 2003 :

n  A Power-Ware SWRD Cell for Reducing Cache Write Power, Y.-J. Chang, C.-L. Yang and F.-P. Lai, in Proceedings of the IEEE International Symposium on Low Power Electronics and Design.(ISPLED '03), Seoul, Korea, August, 2003 : 14-17

n  Using Intel Streaming SIMD Extensions for 3D Geometry Processing, W. Ma and C.-L. Yang, in Proceedings of the 3th IEEE Pacific-Rim Conference on Multimedia (PCM '02), Springer-Verlag, Taiwan, December, 2002 : 1080-1087

n  A Programmable Memory Hierarchy for Prefetching Linked Data Structures, C.-L. Yang and A. R. Lebeck, in Proceedings of the 4th International Symposium on High Performance Computing (ISHPC-IV),  Springer-Verlag, Japan, May, 2002 : 160-174

n  Push vs. Pull: Data Movement for Linked Data Structures, C.-L. Yang and A. R. Lebeck, in Proceedings of  International Conference on Supercomputing (ICS '00), May, 2000 : 176-186

n  Annotated Memory References: A Mechanism for Informed Cache Management, A. R. Lebeck, D. R. Raymond, C.-L. Yang, M. S. Thottethodi, in Proceedings of  Euro-Par '99, August, 1999. (Short Version) 1251-1254

n  Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications, C.-L. Yang, B. Sano, and A. R. Lebeck,  in Proceedings of ACM/IEEE International Symposium on Microarchitecture (MICRO '98), November, 1998 :  14-24

Journal PUBLICATION

n  Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling, Li-Jhan Chen, Hsiang-Yun Cheng, Po-Han Wang, Chia-Lin Yang, IEEE Computer Architecture Letters, 16(2): 127-131 (2017)

n  Exploiting Write Heterogeneity of Morphable MLC/SLC SSDs in Datacenters with Service-Level Objectives, Che-Wei Chang, Geng-You Chen, Yi-Jung Chen, Chia-Wei Yeh, Pei Yin Eng, Ana Cheung, Chia-Lin Yang, IEEE Trans. Computers, 66(8): 1457-1463 (2017)

n  A Hybrid DRAM/PCM Buffer Cache Architecture for Smartphones with QoS Consideration, Ye-Jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang, ACM Trans. Design Autom. Electr. Syst. 22(2): 27:1-27:22 (2017)

n  Improving ReadPerformance of NAND Flash SSDs by Exploiting Error Locality, Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li,  IEEE Trans. Computers, 65(4): 1090-1102 (2016)

n  System-Level Performance and Power Optimization for MPSoC - A Memory-Access Aware Approach, Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Tay-Jyi Lin, Chih-Wen Hsueh, Naehyuck Chang, ACM Transcations on Embedded Computing System, 14(1): 8:1-8:26 (2015)

n  SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs, Chung-Hsiang Lin, De-Yu Shen, Yu-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang, ACM Transaction on Computer Architecture and Code Optimization, 12(2): 19:19:1-19:19:24 (2015)

n  Power Gating Strategies on GPUs, Po-Han Wang, Chia-Lin Yang, Yen-Ming Chen and Yu-  Jung Cheng, in ACM Transactions on Architecture and Code Optimizations, 8(3): 13:1-13:25 (2011)

n  Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling, Mizunuma H, Yi-Chang Lu and Chialin Yang, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(9): 1293-1306 (2011)

§ TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems, Yi-Jung Chen, Chia-Lin Yang, Jaw-Wei Chi and Jian-Jia Chen, in IEEE Transactions on Computers, 60(6): 767-782 (2011)

§ A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips, P.-H. Yuh, Sachin Sapatnekar, C.-L. Yang, Y.-W. Chang, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(9): 1295-1306(2009)

§ Leakage-aware Task Scheduling for Partially Dynamically Reconfigurable FPGAs, P.-H. Yuh,  C.-L. Yang, C.-F. Li, C.-H. Lin, in ACM Transactions on Design Automation of Electronic Systems (TODAES), 14(4): 52:1-52:26 (2009)

§ T-trees: A Tree-Based Representation for Temporal and Three-Dimensional Floorplanning, P.-H. Yuh,   C.-L. Yang, Y.-W. Chang, in ACM Transactions on Design Automation of Electronic Systems (TODAES), 14(4): 51:1-51:28 (2009)

§ An Architectural Co-Synthesis Algorithm for Energy-Aware Network-on-Chip Design, Y.-J. Chen, C.-L. Yang and Y.-S. Chang, in Journal of Systems Architecture, 55(5-6): 299-309  (2009)

§ A Predictive Shutdown Technique for GPU Shader Processors, P.-H. Wang, Y.-M. Chen, C.-L. Yang and Y.-J. Cheng, in IEEE Computer Architecture Letters, 8(1): 9-12 (2009)

§ A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters, S.-W, Wang, S.-S Yang, H.-M, Chen, C.-L, Yang, W.-J, Ling, in Journal Signal Processing Systems, 57(2): 195-211 (2009)

n  Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs, Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang, IEEE Trans. on CAD of Integrated Circuits and Systems, 27(4): 643-653 (2008)

§ BioRoute: A Network-Flow Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips, P.-H. Yuh, C.-L. Yang, and Y.-W. Chang, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(11): 1928-1941 (2008)

§ Energy-Aware Flash Memory Management in Virtual Memory System, L.-H. Lin, C.-L. Yang, H.-W., Tseng, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16(8): 952-964 (2008)

§ Placement of Defect-Tolerant Digital Microfluidic Biochips, P.-H. Yuh, C.-L. Yang, and Y.-W. Chang, in ACM Journal on Emerging Technologies in Computing Systems (JETC), 3(3): 13 (2007)

§ Temporal Floorplanning Using the Three Dimensional Transitive Closure SubGraph, P.-H. Yuh, C.-L. Yang, and Y.-W. Chang, in ACM Transaction on Design Automation of Electronic Systems (TODAES), 12(4): 37 (2007)

§ Software-Controlled Cache Architecture for Energy Efficiency, C.-L. Yang, H.-W. Tseng, C.-C. Ho, J.-L. Wu, in IEEE Transaction on Circuits and Systems for Video Technology, 15(5): 634-644  (2005)

§ Tolerating Memory Latency Through Push Prefetching for Pointer-Intensive Applications, C.-L. Yang, A. R. Lebeck, H.-W. Tseng, and C.-H. Lee, in ACM Transacations on Architecture and Code Optimization, 1(4): 445-475 (2004)

§ Zero-Aware Asymmetric SRAM Cell for Reducing Cache Power in Writing Zero, Y,-J, Chang, F. Lai and C.-L Yang, in IEEE Transactions on Very Large Intergration (VLSI) Systems, 12(8): 827-836 (2004)

§ Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions, C.-L. Yang, B. Sano, and A. R. Lebeck, in IEEE Transactions on Computers, 49(9): 934-946 (2000)